Comments
Continuing on the theme of using machine learning to speed up
electromagnetic simulations, we've got some new work to share! This
paper goes beyond the 2D example previously explored and now looks at
full-wave 3D solutions
. Most importantly, we wanted to show that this
is possible with geometry generalizations. For example, many papers
pass things like via drill diameter and other parameters directly as
input to their
neural networks
. We instead mesh the geometry into a 3D
rectangular grid and pass this as input to the
neural network
instead. The result was quite impressive!
read more
Comments
Some initial research points to yes, for certain applications. Here's a
preview of a paper I'll be sharing at this year's
IEEE
EMC
+
SIPI
conference in Spokane. There's still a lot of work to be done, and I'm
admittedly quite a
machine learning
amateur. Even so, I think there
are areas in
signal integrity
where we can find smart ways to apply
machine learning
to speed up design cycle time.
read more
Comments
A few months ago, I had the wonderful privilege of presenting a
webinar with the great team at Nine Dot Connects (NDC). I've been a
huge fan of NDC ever since I first started learning Altium at my first
job out of undergrad, so I was thrilled to be asked to work with
them. The webinar goes over some important PCB stackup design aspects
which are crucial for successful high-speed digital design.
read more
Comments
I recently presented (another) webinar with EMA Design Automation to
discuss
DDR5
! This time the discussion was centered around a live
post-layout demo. In the example, I showed the analysis of a board
with
PowerSI
(which, of course, had some failures when the DDR report
was generated). We then used
S-parameter
and
TDR
analysis to track down
the failures. Lastly, we used the
Clarity
Via Wizard to generate new
via models and we used
Allegro
High-Speed Structures to place them in
the layout. Lastly, the board was verified to show a passing report.
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Comments
I recently presented a webinar with EMA Design Automation to discuss
DDR5
! I cover the new features added compared to
DDR4
then spend some
time showing a demo of Cadence
Topology Explorer
(
TopXp
) including
simulation of a full byte lane with
IBIS-AMI
models.
read more
Comments
I recently presented a webinar with EMA Design Automation to explain
some common signal and power integrity problems that I've
encountered. All of these issues are ones which I've dealt with in the
past, and each one shows how ECAD tools can be used to find and fix
them before sending a design out for manufacturing. Specifically, each
example uses the new Sigrity Aurora analysis features embedded
directly within the Cadence PCB Editor, which reduces a lot of the
back-and-forth design/analyze/fix cycle that often occurs.
read more