Webinar Recording: DDR5 Post-Layout Verification: Find and Fix Causes of Failure
CommentsI recently presented (another) webinar with EMA Design Automation to discuss DDR5 ! This time the discussion was centered around a live post-layout demo. In the example, I showed the analysis of a board with PowerSI (which, of course, had some failures when the DDR report was generated). We then used S-parameter and TDR analysis to track down the failures. Lastly, we used the Clarity Via Wizard to generate new via models and we used Allegro High-Speed Structures to place them in the layout. Lastly, the board was verified to show a passing report.
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