Webinar Recording: DDR5 Post-Layout Verification: Find and Fix Causes of Failure

Webinar Recording: DDR5 Post-Layout Verification: Find and Fix Causes of Failure

I recently presented (another) webinar with EMA Design Automation to discuss DDR5! This time the discussion was centered around a live post-layout demo. In the example, I showed the analysis of a board with PowerSI (which, of course, had some failures when the DDR report was generated). We then used S-paramter and TDR analysis to track down the failures. Lastly, we used the Clarity Via Wizard to generate new via models and we used Allegro High-Speed Structures to place them in the layout. Lastly, the board was verified to show a passing report.

DDR5 represents a significant performance improvement to the DDR interface over DDR4 with data transfer rates going from 3200 MT/s to as much as 8400 MT/s according to the JEDEC spec. With this increased performance comes architectural changes that must be understood to effectively design and leverage these next generation memory devices. These changes also require updated simulation techniques and methodologies to ensure accurate and effective characterization of the DDR5 interface.

The slides and recording are available at the EMA website, or watch the video below.




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