## Can Machine Learning Replace Field Solvers?

Update I'm happy to report that this paper was a Best SIPI Paper finalist at the conference! While I was unable to attend in-person due to a missed flight, the paper has been published to IEEE Xplore here. — Some initial research points to yes, for certain applications. Here's a preview of a paper I'll be sharing at this year's IEEE EMC+SIPI conference in Spokane. There's still a lot of work to be done, and I'm admittedly quite a machine learning amateur. Even so, I think there are areas in signal integrity where we can find smart ways to apply machine learning to speed up design cycle time.

## PCB Stackup Webinar with Nine Dot Connects

A few months ago, I had the wonderful privilege of presenting a webinar with the great team at Nine Dot Connects (NDC). I've been a huge fan of NDC ever since I first started learning Altium at my first job out of undergrad, so I was thrilled to be asked to work with them. The webinar goes over some important PCB stackup design aspects which are crucial for successful high-speed digital design. We present some information, and then go over a real-world stackup design example using the wonderful Simbeor electromagnetic simulation software. I'm a huge fan of Simbeor as one of the best tools on the market for pre-layout design work.

## Webinar Recording: DDR5 Post-Layout Verification: Find and Fix Causes of Failure

I recently presented (another) webinar with EMA Design Automation to discuss DDR5! This time the discussion was centered around a live post-layout demo. In the example, I showed the analysis of a board with PowerSI (which, of course, had some failures when the DDR report was generated). We then used S-paramter and TDR analysis to track down the failures. Lastly, we used the Clarity Via Wizard to generate new via models and we used Allegro High-Speed Structures to place them in the layout. Lastly, the board was verified to show a passing report. DDR5 represents a significant performance improvement to the DDR interface over DDR4 with data transfer rates going from 3200 MT/s to as much as 8400 MT/s according to the JEDEC spec.

## Webinar Recording: A Dive into DDR5: An Engineers Guide to Simulating and Validating the Latest Generation of DDR

I recently presented a webinar with EMA Design Automation to discuss DDR5! I cover the new features added compared to DDR4 then spend some time showing a demo of Cadence Topology Explorer (TopXp) including simulation of a full byte lane with IBIS-AMI models. DDR5 represents a significant performance improvement to the DDR interface over DDR4 with data transfer rates going from 3200 MT/s to as much as 8400 MT/s according to the JEDEC spec. With this increased performance comes architectural changes that must be understood to effectively design and leverage these next generation memory devices. These changes also require updated simulation techniques and methodologies to ensure accurate and effective characterization of the DDR5 interface.

We've all been there: you've got a problem to solve and are faced with the make versus buy decision. In my case, I wanted to switch a USB peripheral between two PCs; that's the only hard requirement. The easiest solution would have been to simply add a USB hub to my KVM switch and call it a day, but that wouldn't carry USB-3 multi-gigabit data rates (not that I needed to, but I wanted to). Even still, nearly identical products do already exist and can be bought for as cheap as $15 USD1, but where's the fun in that? ## The Quickest Antenna Design of the Year During a recent weekend, I found myself with some parts laying around which I hadn't used in quite a while. First in the bin was an old Orange Pi One1 (an underpowered SBC similar to the Raspberry Pi) which I was going to use to run a video conferencing screen but which proved to be unable to run the graphical Linux installation well enough to be usable. My RTL-SDR2 stick also happened to be out (I can't actually remember why I grabbed it a few weeks ago for the first time in years). As I cleaned everything up and got ready to put it away, I realized that I was probably never going to use this stuff again, so instead of trashing it I decided to put it to good use! ## Webinar Recording: 6 Common SI/PI Issues Lurking in Your Design And How to Prevent Them I recently presented a webinar with EMA Design Automation to explain some common signal and power integrity problems that I've encountered. All of these issues are ones which I've dealt with in the past, and each one shows how ECAD tools can be used to find and fix them before sending a design out for manufacturing. Specifically, each example uses the new Sigrity Aurora analysis features embedded directly within the Cadence PCB Editor, which reduces a lot of the back-and-forth design/analyze/fix cycle that often occurs. The slides and recording are available at the EMA website, or watch the video below. ## IIoT Low Power Software and Hardware Considerations Shield Digital Design and MAB Labs have collaborated to publish a white paper describing both hardware and software methods of reducing power consumption for an Industrial IoT (IIoT) wirelessly networked device. ## The Mystery Misfire The dreaded P0171 code… If you've experienced it, just the mention likely gives you nightmares. If not - here's the rundown. P0171 is the automotive On-Board Diagnostics (OBD) code1 for a lean condition on the engine. If the engine is running lean, it simply means that the air to fuel ratio is not optimized, and there's either too much air or not enough fuel. Before I get too far ahead here, let's set the scene. Routine Tune Up We've all been there - time for a little routine maintenance on the car. Oil change, check the fluids and filters, basic tune up… oh and the last mechanic said the spark plugs need to be changed. ## Parallel Plate Capacitor Equation - Simulated The Question A recent homework problem had us derive the parallel plate capacitor1 equation for electrostatics. This gives the capacitance of a parallel plate structure in terms of the plate area, distance between the plates and relative permittivity. The equation for this situation is:$ C = \epsilon_{R}\epsilon_{0}\frac{A}{d} \$ After solving this problem for the analytical solution, I was curious to see how closely the result matched a 3D field solver. Using the Capacitance Extraction mode in Cadence 3D Workbench, I designed a parametric model of the parallel plate capacitor with variable edge length, distance and dielectric constant (See image above for the model).

### Want to chat about hardware?

I love talking about electrical engineering, signal & power integrity, PCB design/simulation or any other topic. Reach out to me any time.