Comments
I recently presented (another) webinar with EMA Design Automation to
discuss
DDR5
! This time the discussion was centered around a live
post-layout demo. In the example, I showed the analysis of a board
with
PowerSI
(which, of course, had some failures when the DDR report
was generated). We then used
S-parameter
and
TDR
analysis to track down
the failures. Lastly, we used the
Clarity
Via Wizard to generate new
via models and we used
Allegro
High-Speed Structures to place them in
the layout. Lastly, the board was verified to show a passing report.
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Comments
I recently presented a webinar with EMA Design Automation to discuss
DDR5
! I cover the new features added compared to
DDR4
then spend some
time showing a demo of Cadence
Topology Explorer
(
TopXp
) including
simulation of a full byte lane with
IBIS-AMI
models.
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Comments
We've all been there: you've got a problem to solve and are faced with
the make versus buy decision. In my case, I wanted to switch a USB
peripheral between two PCs; that's the only hard requirement. The
easiest solution would have been to simply add a USB hub to my
KVM switch
and call it a day, but that wouldn't carry USB-3 multi-gigabit
data rates (not that I needed to, but I wanted to).
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Comments
I recently presented a webinar with EMA Design Automation to explain
some common signal and power integrity problems that I've
encountered. All of these issues are ones which I've dealt with in the
past, and each one shows how ECAD tools can be used to find and fix
them before sending a design out for manufacturing. Specifically, each
example uses the new Sigrity Aurora analysis features embedded
directly within the Cadence PCB Editor, which reduces a lot of the
back-and-forth design/analyze/fix cycle that often occurs.
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