Topic

Ddr

Feb 3, 2022 1 min read #Ecad #Cadence #Webinar #Signal integrity #Simulation #Ddr

Webinar Recording: DDR5 Post-Layout Verification: Find and Fix Causes of Failure

I recently presented (another) webinar with EMA Design Automation to discuss DDR5 ! This time the discussion was centered around a live post-layout demo. In the example, I showed the analysis of a board with PowerSI …

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Jan 8, 2022 1 min read #Ecad #Cadence #Webinar #Signal integrity #Simulation #Ddr

Webinar Recording: A Dive into DDR5: An Engineers Guide to Simulating and Validating the Latest Generation of DDR

I recently presented a webinar with EMA Design Automation to discuss DDR5 ! I cover the new features added compared to DDR4 then spend some time showing a demo of Cadence Topology Explorer ( TopXp ) including simulation …

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