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PCB Stackup Webinar with Nine Dot Connects

A few months ago, I had the wonderful privilege of presenting a webinar with the great team at Nine Dot Connects (NDC). I've been a huge fan of NDC ever since I first started learning Altium at my first job out of undergrad, so I was thrilled to be asked to work with them. The webinar goes over some important PCB stackup design aspects which are crucial for successful high-speed digital design. We present some information, and then go over a real-world stackup design example using the wonderful Simbeor electromagnetic simulation software. I'm a huge fan of Simbeor as one of the best tools on the market for pre-layout design work.

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Webinar Recording: DDR5 Post-Layout Verification: Find and Fix Causes of Failure

I recently presented (another) webinar with EMA Design Automation to discuss DDR5! This time the discussion was centered around a live post-layout demo. In the example, I showed the analysis of a board with PowerSI (which, of course, had some failures when the DDR report was generated). We then used S-paramter and TDR analysis to track down the failures. Lastly, we used the Clarity Via Wizard to generate new via models and we used Allegro High-Speed Structures to place them in the layout. Lastly, the board was verified to show a passing report. DDR5 represents a significant performance improvement to the DDR interface over DDR4 with data transfer rates going from 3200 MT/s to as much as 8400 MT/s according to the JEDEC spec.

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Webinar Recording: A Dive into DDR5: An Engineers Guide to Simulating and Validating the Latest Generation of DDR

I recently presented a webinar with EMA Design Automation to discuss DDR5! I cover the new features added compared to DDR4 then spend some time showing a demo of Cadence Topology Explorer (TopXp) including simulation of a full byte lane with IBIS-AMI models. DDR5 represents a significant performance improvement to the DDR interface over DDR4 with data transfer rates going from 3200 MT/s to as much as 8400 MT/s according to the JEDEC spec. With this increased performance comes architectural changes that must be understood to effectively design and leverage these next generation memory devices. These changes also require updated simulation techniques and methodologies to ensure accurate and effective characterization of the DDR5 interface.

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Webinar Recording: 6 Common SI/PI Issues Lurking in Your Design And How to Prevent Them

I recently presented a webinar with EMA Design Automation to explain some common signal and power integrity problems that I've encountered. All of these issues are ones which I've dealt with in the past, and each one shows how ECAD tools can be used to find and fix them before sending a design out for manufacturing. Specifically, each example uses the new Sigrity Aurora analysis features embedded directly within the Cadence PCB Editor, which reduces a lot of the back-and-forth design/analyze/fix cycle that often occurs. The slides and recording are available at the EMA website, or watch the video below.

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