Do you have an application with a TO-220 linear regulator that you’d like to replace with a switching power supply for improved efficiency?
The SDP101 series power modules are now available starting with the 3.3V output device. These modules feature a simple three-pin design (VIN, GND, VOUT) and are compatible with most TO-220 linear regulators. With a max operational input voltage of 5.5V and standard fixed outputs of 3.3V, 2.5V, 1.8V, 1.2V, and 1.0V these will surely find quick use in the lab or in your next product. Custom fixed voltages available upon request.
Shield Digital Design is proud to announce our latest product: the PMOD compatible Time-of-Flight Laser Distance Sensor based on the ST Micro VL53L0X. The sensor has a range of up to 2m, and included both the right-angle header as well as straight header for flexible use. (The VL53L0X is mounted to the bottom of the board such that it would face away from the development board when used with a straight header). The 6-Pin PMOD interface includes the I2C bus, shutdown, and an interrupt output.
You might have noticed that VCC and GND are swapped on the photos of the device… the files for the prototype run erroneously flipped the pins on the schematic, but the correct pinout was used for the production devices.
The original idea behind fRISCy was to begin with the FE310 RISC-V microcontroller, mate it with an FPGA for highly configurable processing, and package it in the familiar Raspberry Pi form factor. While the basic premise has not changed, we’ve decided to switch from an Artix-7 FPGA over to a Lattice iCE-40. There were a couple of comments about including the RISC-V microcontroller, but using a closed FPGA, so this change will allow for full development using open source toolchains! Look for updates to the fRISCy page in the next few weeks. Here are a couple more key points about the change:
Attempting to reduce the PCB layer count to 4-layers in an effort to reduce costs
Will keep Ethernet and SYZYGY connectors as they are primary connectivity
Will reduce connections to the FE310. As many IO functions as possible will be handled by the FPGA, with a high-speed SPI interface between the FE310 and FPGA. This will allow the FPGA to simply act as a SPI peripheral to the FE310
I2C to the GPIO header will probably be shared between FPGA and FE310
One RGB LED will remain on the FE310
All other open pins on the FE310 will be routed to the FPGA for use as GPIOs or IRQs