A Way Forward for fRISCy

The original idea behind fRISCy was to begin with the FE310 RISC-V microcontroller, mate it with an FPGA for highly configurable processing, and package it in the familiar Raspberry Pi form factor. While the basic premise has not changed, we’ve decided to switch from an Artix-7 FPGA over to a Lattice iCE-40. There were a couple of comments about including the RISC-V microcontroller, but using a closed FPGA, so this change will allow for full development using open source toolchains! Look for updates to the fRISCy page in the next few weeks. Here are a couple more key points about the change:

  • Attempting to reduce the PCB layer count to 4-layers in an effort to reduce costs
  • Will keep Ethernet and SYZYGY connectors as they are primary connectivity
  • Will reduce connections to the FE310. As many IO functions as possible will be handled by the FPGA, with a high-speed SPI interface between the FE310 and FPGA. This will allow the FPGA to simply act as a SPI peripheral to the FE310
    • I2C to the GPIO header will probably be shared between FPGA and FE310
    • One RGB LED will remain on the FE310
    • All other open pins on the FE310 will be routed to the FPGA for use as GPIOs or IRQs

Original Block Diagram